1. Field of the Invention
The present invention relates to a memory module, and in particular to a memory module optimal for use in a multiple-rank memory system.
2. Description of the Related Art
Memory systems are employed various types of electronic equipment such as personal computers (hereafter, referred to as “PCs”), digital cameras, and printers, and their memory capacity has been increased more and more. One of these memory systems is for example a memory system used in a PC and having a plurality of dual inline memory modules (DIMMs). Each of the DIMMs has terminals on the opposite surfaces of a module board, and is provided with semiconductor memories, a phase-locked loop circuit (PLL) for phase adjustment, a register for supplying a control signal, and so on. The semiconductor memories used here are large-capacity dynamic random access memories (DRAM).
The memory system is optimized for relevant electronic equipment by properly determining a memory capacity, a number of data bits, and a number of ranks, and is provided with a single or a plurality of memory modules. The term “a rank” means a group of memories that can be read and written simultaneously.
FIG. 1 shows a schematic diagram of a three-slot memory system. The memory system includes a motherboard that is provided thereon with a memory controller 1, and a plurality of wirings including data or data strobe (DQ/DQS) signal lines 2 and clock (CLK) signal lines 3. Because data, data strobe and clock signals are differential or complementary signals, the signal lines 2 and 3 are depicted as signal line pairs.
The memory system of FIG. 1 further includes a connector 4 and a DIMM 5 in each slot. The DIMM 5 has a plurality of DRAMs 6, a PLL 7, and a register 8 mounted on the memory module board. The DIMM 5 is also referred to as the “registered DIMM”.
In the memory system shown in FIG. 1, each of the CLK signal lines 3 is connected to one of the DIMMs 5. On the other hand, each of the DQ/DQS signal lines 2 is connected to all of the DIMMs 5 by being branched therefrom. FIG. 2 is a topology diagram illustrating the CLK signal lines 3 in this memory system. FIGS. 3 and 4 are topology diagrams illustrating the DQ/DQS signal lines 2 when one-rank and two-rank DIMMs are used in the memory system, respectively.
As shown in FIG. 2, the CLK signal lines 3 are connected such that a CLK signal is supplied to the PLL 7 of each DIMM 5 from the memory controller 1 via the corresponding pair of CLK signal lines 3 and the corresponding connector 4 on the motherboard.
The DQ/DQS signal lines 2 are branched from the motherboard wirings and connected to the DRAMs 6 of the entire DIMMs 5 via the respective connectors 4. In the case of the one-rank DIMMs shown FIG. 3, a DQ/DQS signal is supplied to one DRAM of each DIMM 5. In the case of two-rank DIMMs shown in FIG. 4, a DQ/DQS signal is supplied to two DRAMs (RANK0 and RANK1) of each DIMM. The terms “CLK signal lines 3” and “DQ/DQS signal lines 2” are used herein to generally refer to the wirings including internal wirings of the DIMMs 5.
FIG. 5 shows an example of the CLK signal lines 3 in the registered DIMM 5, and FIG. 6 shows an example of the DQS signal lines 2 in the registered DIMM 5. As shown in FIG. 5, a CLK signal output from the memory controller 1 is input to the PLL 7 through CLK terminals 11 of the DIMM 5. The CLK signal is buffered by the PLL 7, and input to the register 8 and to the DRAMs 6 mounted on the front and rear surfaces of the DIMM 5. The CLK signal lines 3 connecting between the PLL 7 and the respective DRAMs 6 in the DIMM 5 are equal in length. Feedback wirings having an equal length to the CLK signal lines 3 connecting between the PLL 7 and the DRAMs 6 are provided to check the delay time in the CLK signal lines 3 of the DIMM 5.
On the other hand, a DQS signal output from the memory controller 1 is input to at least one of the DRAMs 6 via corresponding DQS terminals 12 and corresponding stub resistances 13. The CLK signal input to the DRAMs 6 via the PLL 7 is processed by the PLL 7 to enter the DRAMs 6 at the same timing as the timing when the CLK signal enters the PLL 7. Accordingly, it can be considered that the timing of the CLK signal entering the PLL 7 is the same as the timing of the CLK signal entering the DRAMs 6.
When data is written in the DRAM 6, the DRAM 6 latches the written data transmitted by the data signal DQ in response to the data strobe signal DQS. The CLK signal and the DQS signal are complementary signals (CLK and CLKB, DQS and DQSB), respectively, and their timings are decided based on the respective cross points. Deviation of the cross points that occurs between the CLK signal and the DQS signal when the DRAM 6 latches data during writing is referred to as tDQSS. The tDQSS can be reworded as “[the difference in flight time (propagation time) from the memory controller to the DRAM between the CLK signal and the DQS signal]+[the deviation of timing when the CLK signal and the DQS signal are output from the controller]”.
The tDQSS is desirably small. This is because a large tDQSS will disable the normal transfer of data from the DQS signal to the CLK signal within the DRAM. According to the standard JEDEC DDR2 specification, therefore, the tDQSS is limited to ±0.25×tCK (tCK denotes one cycle time of the CLK signal), and the tDQSS is ±750 ps in DDR2-667. The specification means that the tDQSS becomes smaller as the operating frequency becomes higher. Therefore, it is crucial to reduce the tDQSS in order to increase the operation speed.
FIG. 7 is an explanatory drawing for explaining relationship among the numbers of DIMMs and ranks forming the memory system and the numbers of CLK and DQS signal loads. Table 1 below shows the numbers of CLK and DQS signal loads. As seen from FIG. 7 and Table 1, in the case (A) of one one-rank DIMM, the number of CLK signal loads is one, and the number of DQ/DQS signal loads is one. In the case (B) of one two-rank DIMM, the number of CLK signal loads is one, and the number of DQ/DQS signal loads is two. In the case (C) of two two-rank DIMMs, the number of CLK signal loads is one, and the number of DQ/DQS signal loads is four. In the case (D) of one four-rank DIMM, the number of CLK signal loads is one, and the number of DQ/DQS signal loads is four. In the case (E) of two four-rank DIMMs, the number of CLK signal loads is one, and the number of DQ/DQS signal loads is eight.
TABLE 1Number of loads when loadof one one-rank DIMM isCasedefined as 1CLKDQS(A)1 one-rank DIMM11(B)1 two-rank DIMM12(C)2 two-rank DIMMs14(D)1 four-rank DIMM14(E)2 four-rank DIMMs18
FIG. 8 is schematic block diagrams showing the memory systems and signal waveform diagrams thereof. The load of the CLK signal is not changed from the number of loads F/O=1 even if the number of the DIMMs inserted into the slots or the number of ranks of DIMMs is increased. In contrast, the load of the DQS signal is increased as F/O=1, 2, 4 onwards along with the increase of the number of DIMMs or the number of ranks of the DIMMs. Accordingly, the DQS signal is delayed by tDQSS1 relative to the CLK signal when the number of loads is one, delayed by tDQSS2 when the number of loads is two, and by tDQSS3 when the number of loads is four.
In general, the same motherboard is used even after various configuration factors of the memory system (e.g., the number of DIMMs and the number of ranks) have been changed. Therefore, the slew rate (gradient) of the DQS waveform becomes low (the waveform deteriorates) as the number of DIMMs and/or the number of ranks is increased, and the timing at the cross point is delayed. However, since the load of the CLK signal is not changed, the waveform of the CLK signal is not changed and the timing at the cross point is not delayed. As a result, the tDQSS is increased along with the increase of the number of DIMMs and/or the number of ranks, eventually exceeding the tDQSS specification that becomes more severe along with the increase of the operation speed. This may result in breakage of the memory system.
The following three patent publications disclose prior arts relating to a memory system having a memory module. Japanese Laid-Open Patent Publication No. 2004-70800 (Patent Publication 1) discloses a technique in which timing of clocks CLK input to a PLL, a register, and DRAMs is adjusted such that a margin of command and address setup time before the CLK is equal to that of command and address hold time after the CLK. Japanese Patent KOHYO Publication NO. 2004-531981 (published Japanese patent translation of PCT application) (Patent Publication 2) discloses a technique in which a clock CLK is delayed by phase data derived from a data strobe signal DQS. Japanese Laid-Open Patent Publication No, 2005-78547 (Patent Publication 3) discloses a technique in which delay of a DQS signal relative to an internal clock signal is determined to synchronize data DQ to an internal clock.
Additionally, Japanese Laid-Open Patent Publication No. 2004-138480 (Patent Publication 4) discloses a test system which is design to eliminate effect of wiring impedance in an LSI tester and a performance board by inputting a data signal at a clock to a first-stage register from a clock selection circuit. Japanese Laid-Open Patent Publication No. H11-191019 (Patent Publication 5) discloses a clock driver circuit which detects waveform deterioration in an output and changes its drive capacity.
These Patent Publications describe various techniques relating to synchronization to the clock and techniques to correct the output waveform. However, these clock synchronization techniques involve detecting a phase difference, and thus require a circuit for this purpose. None of these Patent Publications describe a technique relating to synchronization to a device to which a clock signal is input, or a technique suggesting solutions of the present invention.
According to the conventional techniques as described above, the tDQSS is increased along with the increase of the number DIMMs and/or the number of ranks, eventually exceeding the tDQSS specification that becomes more severe along with the increase of the operation speed, and resulting in breakage of the memory system.